Method of manufacture of a crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor

ABSTRACT

A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold. Deposit a bulk or a thin film second monolithic conductive layer into the cavity to form a monolithic capacitor core with counterpart cantilevered ribs.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to capacitors for DRAMs and moreparticularly to lower electrodes of crown capacitors with fins or tolower electrodes of stack capacitors.

[0003] 2. Description of Related Art

[0004] U.S. Pat. No. 5,208,180 of Gonzalez shows a “Method of Forming aCapacitor” using a oxide etching process.

[0005] U.S. Pat. No. 5,532,182 of Woo for a “Method for FabricatingStacked Capacitor of a DRAM Cell” shows a fin type capacitor using dopedand undoped amorphous Si layers.

[0006] U.S. Pat. No. 5,573,967 of Tseng describes a “Method for MakingDynamic Random Access Memory with Fin-type Stacked Capacitor”.

[0007] U.S. Pat. No. 5,631,184 of lkemasu et al. describes a “Method ofProducing a Semiconductor Device Having a Fin-type Capacitor.”

[0008] U.S. Pat. No. 5,637,523 of Fazan describes a “Method for Forminga Capacitor and a Capacitor Structure” shows a in type capacitor formedby etching doped and undoped polysilicon layers.

[0009] U.S. Pat. No. 5,656,536 of Wu describes a “Method ofManufacturing a Crown Shaped Capacitor with Horizontal Fins for HighDensity DRAMS.”

SUMMARY OF THE INVENTION

[0010] A fin structure can be made by alternately depositing siliconnitride (Si₃N₄) and silicon dioxide (SiO₂) and dipping back and thenfilling with a polysilicon layer which is a complicated process.

[0011] A crown or stack capacitor with a fin structure is made with adifferent silicon dioxide etching rate in a vapor of hydrogen fluorideHF acid environment.

[0012] This invention teaches a method of forming a fin structure usinga combination of both doped and undoped silicon dioxide layers with abulk or a thin film second conductive layer formed into a capacitorcore. The core can be composed of a monolithic body of conductivematerial.

[0013] In accordance with this invention, a process of forming anelectrode comprises the steps of formation of a capacitor core formed ona semiconductor device which contains doped regions in the surfacethereof blanketed with a dielectric layer which contains a conductiveplug extending therethrough which contacts one of the doped regions inthe semiconductor substrate.

[0014] First, form a sublayer comprising a first conductive layer incontact with a plug which contacts one of the doped regions in thesemiconductor substrate. Form a mold from a stack of silicon dioxidelayers which are alternatingly an undoped layer covered with a dopedlayer on the sublayer comprising the first conductive layer with thestack comprising a bottom layer formed on top of the sublayer and eachadditional layer in the stack formed on a previous one of the layers inthe stack. Pattern the silicon dioxide layers in the mold which arealternatingly doped and undoped to form an intercore,capacitor-core-shaping cavity in the stack of silicon dioxide layersreaching down through the stack to be bottom of the stack. Performdifferential etching of the silicon dioxide layers in the mold. Formundercut edges in the doped silicon dioxide layers with the undopedsilicon dioxide layers having cantilevered ribs projecting from thestacks into the cavity to complete the mold. Deposit a layer ofpolysilicon into the cavity forming a capacitor core with counterpartribs cantilevered (projecting) with a complementary pattern to the moldand the capacitor core having a top surface. Polish the capacitor coreto remove the top surface of the core, and remove the mold.

[0015] Preferably, the mold is etched with a combination of hydrogenfluoride vapor and water vapor.

[0016] In one embodiment, the core is formed of a solid deposit of asecond conductive layer which fills the cavity. The dopant comprisesboron and phosphorus and the mold is etched with a combination ofhydrogen fluoride vapor and water vapor.

[0017] Preferably, the dopant comprises boron and phosphorus, and themold is etched with a combination of hydrogen fluoride vapor and watervapor.

[0018] The core is planarized by a CMP process which removes a topundoped layer of the mold whereby the core has a flat upper surface witha rib located on top of the core, and etch back the sublayer comprisinga first thin conductive layer to separate the core from adjacent cores.

[0019] Alternatively one can deposit a thin layer of a second conductivelayer such as polysilicon into the cavity. Then, form a thin capacitorcore with an array of counterpart cantilevered (projecting) ribs with apattern which is complementary to the pattern of the mold. The capacitorcore has a top surface.

[0020] In the case of the thin layer of the second conductive layer,next deposit a photoresist layer into the inner cavity filling the innercavity. Then polish the capacitor core to remove the top surface of thecore, and remove the photoresist and remove the mold.

[0021] Then etch back the sublayer comprising a first thin conductivelayer to separate the core from adjacent cores.

[0022] Preferably, the core is a monolithic core.

[0023] In accordance with another aspect of this invention, a monolithiccapacitor core is formed on a semiconductor device. A sublayercomprising a first conductive layer is formed in contact with a plugwhich contacts a doped first conductive region in the semiconductorsubstrate. A second conductive layer is formed into a monolithiccapacitor core having cantilevered ribs projecting from exteriorsidewalls of the monolithic core. The monolithic capacitor core has acantilevered top surface projecting from the exterior sidewall of themonolithic core.

[0024] Preferably the second conductive layer is formed into a hollowmonolithic capacitor core having cantilevered ribs projecting fromexterior sidewalls of the monolithic core and a base covering the firstconductive layer. It that case it is preferred that the secondconductive layer formed into a monolithic core is composed of a materialselected from the group consisting of aluminum, copper, tungsten, dopedpolysilicon, and titanium nitride, and said second conductive layer hasa thickness from about 500 Å to about 1,000 Å.

[0025] Alternatively, the second conductive layer is formed as a solidmonolithic capacitor core having cantilevered ribs projecting fromexterior sidewalls of the monolithic core and the core covering thefirst conductive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The foregoing and other aspects and advantages of this inventionare explained and described below with reference to the accompanyingdrawings, in which:

[0027]FIG. 1 shows a sectional vertical elevation of a fragment of asemiconductor device with a first conductive layer formed on the topsurface in an intermediate stage of fabrication of a device inaccordance with this invention.

[0028]FIG. 2 shows the device of FIG. 1 after formation of sacrificialstructures which are to serve as molds with monolithic capacitor corecavities formed of stacks of laminated, blanket layers formed over thefirst conductive layer.

[0029]FIG. 3 shows a first embodiment of the device of FIG. 2 after thinfilm monolithic crown capacitor cores have been formed in the cavitieson the sidewalls of the stacks of laminated, blanket layers formed overthe first conductive layer. Photoresist fills the hollow spaces withinthe monolithic capacitor cores.

[0030]FIG. 4 shows the device of FIG. 3 after the monolithic capacitorcores have been polished down, the molds have been removed, and thefirst conductive layer has been etched in a self-aligned etch.

[0031]FIG. 5 shows a second embodiment of the device of FIG. 2 aftersolid stack monolithic capacitor cores have been formed in the cavitiesover the first conductive layer.

[0032]FIG. 6 shows the device of FIG. 5 after the monolithic capacitorcores have been polished down, the molds have been removed, and thefirst conductive layer has been etched in a self-aligned etch.

DESCRIPTION OF STRUCTURE ANCILLARY TO THE PREFERRED EMBODIMENT

[0033]FIG. 1 shows a sectional vertical elevation of a fragment of asemiconductor device 10 in an intermediate stage of fabrication of adevice in accordance with this invention. A P-doped siliconsemiconductor substrate 12 is shown with N+ doped regions 14 and 14′formed in the surface of the substrate 12 and spaced on opposite ends ofthe portion of substrate 12 shown in FIG. 1. Four gateelectrode/conductor stacks 21A-21D are shown on the surface of substrate12 with the stack 21A formed on the surface of an N+ doped region 14 andstack 21D formed on the surface of an N+ doped region 14′.

[0034] The stacks 21A-21D include gate oxide regions GOX on whichpolysilicon conductor/gate electrode layers 16 are formed on the surfaceof substrate 12. On each of the gate oxide regions GOX is a refractorymetal silicide layer 19 such as tungsten silicide (WSi₂), a cap layerusually composed of silicon dioxide (SiO₂) layer 20 and a siliconnitride (Si₃N₄) layer 22 which can be implemented, as is well understoodby those skilled in the art and as is described in the U.S. Pat. No.5,792,689 of Fu-Lian Yang and Erik S. Jeng for “Method for ManufacturingDouble Crown Capacitors Self-Aligned to Node Contacts on Dynamic RandomAccess Memory”.

[0035] Silicon dioxide sidewall spacers SP are formed on the sidewallsof the layers 16, 19, 20 and 22 of stacks 21A-21D as described in Liawet al U.S. Pat. No. 5,712,202. Layers 20, 22 and spacers SP insulate thelayers 16/19 from the polysilicon plugs PL which are formed betweenstacks 21A/21B and 21C/21D which reach the capacitor node contacts whereplugs PL are formed on the surface of P-substrate 12.

[0036] There are doped regions 14 and 14′ in the surface of thesubstrate 12 having top surfaces to which the plugs PL1 and PL2respectively make electrical and mechanical contact, as in Liaw et alU.S. Pat. No. 5,712,202 and in Yang et al U.S. Pat. No. 5,792,689.

[0037] A planarizing insulating layer 24 composed of BPSG has beenformed as described in Liaw et al U.S. Pat. No. 5,712,202 covering thestacks 21A-21D and the substrate 12, but capacitor node contact openingshave been formed between the sidewall spacers SP of stacks 21A and 21Bon the left and between the sidewall spacers SP of stacks 21C and 21D onthe right and those openings have been filled with metal, conductiveplugs PL1/PL2 extending from contact with the N+ doped regions 14/14′respectfully on the surface of the substrate 12 between the stacks21A/21B and between the stacks 21C/21D to the top surface of the BPSGlayer 24.

DESCRIPTION OF THE PREFERRED EMBODIMENT Step 1

[0038] Above the BPSG layer 24 and plugs PL1/PL2 a doped, thin firstconductive layer/sublayer SL composed of doped polysilicon is formed onthe surface of the device 10 of FIG. 1. In step 1, after the capacitornode contact and polysilicon plugs PL1/PL2 are formed a thin polysiliconsublayer comprising a first conductive layer SL is deposited which canbe implanted with arsenic with a dose in the range from about 1E20 to1E22 ions/cm² and an energy between 30 keV and 45 keV thus giving thefirst conductive layer SL SL a dopant concentration from about 1E20ions/cm³ to 1E22 ions/cm³. Preferably, the first conductive layer SL SLhas a thickness from about 5000 Å to about 10,000 Å with a preferablethickness of about 8,000 Å.

Step 2

[0039] Referring to FIG. 2, the device of FIG. 1 is shown afterformation of molds (sacrificial structures) SS1, SS2 and SS3 formed of astack of laminated, blanket layers formed over first conductive layer SLSL. The molds SS1, SS2 and SS3 comprise undoped silicon dioxide (SiO₂)layer 28A-28D alternating with SiO₂ layers 30A-30C which are doped withBoron/Phosphorus (B/P) dopant to form a doped glass dielectric, i.e.BPSG. The sequence is to form an undoped SiO₂ layer 28B on the bottom,then form a BPSG layer 30B, covered in turn with an undoped SiO₂ layer28C, followed by BPSG layer 30C and topped with undoped SiO₂ layer 28D.The alternating laminated layers 28A-28D and 30A-30C are formed in situin a CVD chamber alternately, by depositing one of the undoped oxidelayers 28A-28D, followed by depositing one of the BSPG layers 30A-30C inthe same chamber of the CVD equipment in a continuous, uninterruptedprocess by periodically opening and closing the B/P dopant source in aCVD chamber as is described below, and as will be well understood bythose skilled in the art.

[0040] Step 2 involves depositing undoped oxide blanket layers28A/28B/28C/28D and boron/phosphorous doped silicon oxide blanket layers30A/30B/30C alternately in the same chamber of the CVD equipment byopening and closing the B/P dopant source in a periodic way to form SiO₂layers 28A/28B/28C/28D alternating with BPSG glass layers 30A/30B/30C.

Step 3

[0041] Then patterning mask sections PR1/PR2/PR3 with windows W1 and W2therebetween are formed over the layer 28D on top of the blanketlaminated layers 28A/30A/28B/30B/28C/30C/28D of SiO₂ alternating withBPSG glass layers. The layers 28A/30A/28B/30B/28C/30C/28D are thenpatterned into sacrificial molds ST1-ST3 and etched using the masksections PR1/PR2/PR3. The mask sections PR1/PR2/PR3 were used to formmolds to shape the cores of capacitor crowns that are patterned byetching in step 4 below to produce the result shown in FIG. 2 with a setof intercore, capacitor-core-shaping cavities CC1/CC2 formed belowwindows W1 and W2 respectively (to serve as molds for capacitor cores)in FIG. 2, by plasma dry etching between sacrificial structures SS1, SS2and SS3.

[0042] The laminated, sacrificial molds SS1, SS2 and SS3 are shownprotected by patterning photoresist mask sections PR1/PR2/PR3 which wereformed for the purpose of protecting the molds SS1, SS2 and SS3 duringpatterning of the alternating laminated layers 28A-28D and 30A-30C byetching of those laminated layers to form intercore,capacitor-core-shaping cavities CC1 and CC2 above the plugs PL1 and PL2respectively in complementary patterns to the capacitor crowns which areto be formed subsequently as indicated by FIGS. 3 and 4 for the firstembodiment and by FIGS. 5 and 6 for the second embodiment.

[0043] Then the intercore cavities CC1/CC2 (which are to be used assacrificial molds for shaping capacitor cores seen in FIGS. 4 and 6) areformed in the shape of the photoresist mask elements PR1, PR2, and PR3by plasma dry etching between molds (sacrificial structures) SS1-SS3 asdescribed in step 3 below.

[0044] Next, the device is etched again in step 4 to produce theundercuts UC seen in FIG. 2.

Step 4

[0045] A differential rate of etching back the undoped silicon dioxidelayers 28A/28B/28C/28D (slowly) and the doped BPSG layers 30A/30B/30C(more rapidly) is performed to enlarge the intercore,capacitor-core-shaping CC1/CC2 with a vapor solution of hydrogenfluoride (HF). The silicon dioxide and BPSG are etched in an atmosphereof water vapor and hydrogen fluoride (HF) which provides a vaporetchant. The BPSG layers 30A/30B/30C are etched back at a greater ratethan the undoped silicon dioxide layer providing an undercut UC in BPSGglass layers 30A/30B/30C leaving cantilevered ribs CR of SiO₂ layers28A/28B/28C/28D which now project into the intercore cavities CC1/CC2.

[0046] One can tune doped/undoped selectivity by varying theconcentration of hydrogen fluoride HF and water vapor.

First Embodiment

[0047] The first embodiment of the process continues after step 4comprising the following steps:

Step 5A

[0048]FIG. 3 shows the device of FIG. 2 after thin film crown capacitorcores 42A/42B have been formed in the cavities CC1 and CC2 on thesidewalls of stacks SS1-SS3. The cores 42A/42B are preferably monolithicin the sense that they are formed of a single homogeneous, conductive,core layer 40.

[0049] Then a filler layer 41 of a material such as photoresist fillsthe hollow spaces within the capacitor cores 42A/42B.

[0050] In the case of the crown capacitor cores 42A/42B in FIGS. 3,deposit a conformal, thin polysilicon, second conductive, core layer 40into cavity blanketing the top of first conductive layer SL SL andcoating the walls of the molds SS1, SS2 and SS3, as shown in FIG. 3 toform crown capacitor cores 42A/42B from conductive core layer 40,leaving the openings 44 only partially filled by the thin layer ofconductive material 40. Conductive core layer 40 can be composed of anelectrically conductive material selected from the group consisting ofaluminum, copper, tungsten, doped polysilicon, and titanium nitride.Conductive material 40 has a thickness from about 500 Å to about 1,000Å.

Step 6A

[0051]FIG. 4 shows the device of FIG. 3 after the capacitor cores42A/42B have been polished down and the molds have been removed.

[0052] As can be seen in FIG. 4 counterpart cantilevered ribs 40A, 40B,40C have been formed where the cores extend out into the space where theundercut regions UC had been located in the molds SS1, SS2 and SS3.

[0053] The crown capacitor cores 42A/42B in FIG. 4 the openings 44 whichwere filled with filler (photoresist) layer 41 and polished by a CMP(Chemical Mechanical Planarization) process to remove polysilicon layer28D and portion of core layer 40 above the rib 40C.

[0054] Thus, the cores have been planarized by the CMP process whichremoves a top undoped layer 28D of the molds SS1-SS3 whereby the cores42A/42B have a flat upper surface with a rib 40C located on top of eachof the cores 42A/42B.

Step 7A

[0055] First, remove the filler layer 41 (photoresist) in theconventional manner.

[0056] Then, remove the mold formed by silicon dioxide/BPSG layers28A/30A/28B/30B/28C/30C/28D from the inside and the outside of the crowncapacitor cores 42A/42B subtractively in a process which removes theSiO₂ layers 28A/28B/28C/28D and the BPSG glass layers 30A/30B/30C by astep with a Buffered Oxide Etching (BOE) solution which leaves the crownshape with the horizontal fins which consists of the first conductivelayer SL and the second conductive, core layer 40.

[0057] Then dry etch back polysilicon first conductive layer SL SL in aself-aligned etch using the crown capacitor cores 42A/42B as masks toisolate the individual capacitor cores 42A/42B.

Second Embodiment

[0058] The process continues after step 4 comprising the followingsteps:

Step 5B

[0059]FIG. 5 shows a second embodiment of the device of FIG. 2 aftersolid stack capacitor cores 52A/52B have been formed in the cavitiesover the first conductive layer SL. The cores 52A/52B are preferablymonolithic in the sense that they are formed of a single homogeneousmaterial. The capacitor cores 52A/52B of FIGS. 5 are formed from a thickpolysilicon layer 50 blanketing the top of device 10 as shown in FIGS. 5and 6 to form a set of solid stack conductive capacitor cores 52A/52Bformed by of a core layer 50 of conductive material. Layer 50 can becomposed of an electrically conductive material selected from the groupconsisting of aluminum, copper, tungsten, doped polysilicon, andtitanium nitride.

[0060] As can be seen in FIG. 5 counterpart cantilevered ribs 50R havebeen formed where the cores extend out into the space where the undercutregions UC had been located in the molds SS1, SS2 and SS3.

Step 6B

[0061]FIG. 6 shows the device of FIG. 5 after the capacitor cores havebeen polished down, the molds have been removed, and the firstconductive layer has been etched in a self-aligned etch.

[0062] In the case of the thick core layer 50 of FIG. 6 the CMP can beapplied directly to the top of the cores 50 of stack capacitor cores52A/52B to produce the planarized structures 52A/52B, as shown in FIG. 6to remove the portion of core layer 50 above the top of rib 40C.

[0063] Thus, the cores 52A/52B have been planarized by the CMP processwhich removes a top undoped layer 28D of the molds SS1-SS3 whereby thecores 52A/52B have a flat upper surface with a rib 50R located on top ofeach of the cores 52A/52B.

Step 7B

[0064] Next, remove the mold comprising the layers28A/30A/28B/30B/28C/30C/28D of silicon dioxide and BPSG from the insideand the outside of the capacitor structures 52A/52B by a subtractiveprocess which removes the SiO₂ layers 28A/28B/28C/28D by the steps of aBOE process and the BPSG glass layers 30A/30B/30C with by the steps of aBOE process.

[0065] Then etch back polysilicon first conductive layer SL SL in a dryetching such as an RIE process using the capacitor structures 52A/52B asself-aligned masks to isolate the individual capacitor structures52A/52B.

[0066] While this invention has been described in terms of the abovespecific embodiment(s), those skilled in the art will recognize that theinvention can be practiced with modifications within the spirit andscope of the appended claims, i.e. that changes can be made in form anddetail, without departing from the spirit and scope of the invention.Accordingly all such changes come within the purview of the presentinvention and the invention encompasses the subject matter of the claimswhich follow.

Having thus described the invention, what is claimed as new anddesirable to be secured by Letters Patent is as follows:
 1. A process offorming an electrode comprising a capacitor core formed on a conductorsublayer formed on substrate, comprising: forming a mold from a stack ofsilicon dioxide layers which are alternatingly undoped, doped, andundoped on said sublayer with said stack comprising a bottom layerformed on top of said conductor sublayer and each additional layer insaid stack formed on a previous one of said layers in said stack,patterning said silicon dioxide layers in said mold which arealternatingly doped and undoped to form an intercore,capacitor-core-shaping cavity in said stack of silicon dioxide layersreaching down through said stack to be bottom of said stack,differentially etching said silicon dioxide layers in said mold formingundercut edges in said doped silicon dioxide layers with said undopedsilicon dioxide layers having cantilevered ribs projecting from saidstacks into said cavity to complete said mold, deposit a secondconductive layer into said cavity forming a capacitor core withcounterpart cantilevered ribs with a complementary pattern to said moldand said capacitor core having a top surface, polish said capacitor coreto remove said top surface of said core, and remove said mold.
 2. Aprocess in accordance with claim 1 wherein: said mold is etched with acombination of hydrogen fluoride vapor and water vapor.
 3. A process inaccordance with claim 1 wherein: said dopant comprises boron andphosphorus, and said mold is etched with a combination of hydrogenfluoride vapor and water vapor.
 4. A process in accordance with claim 1wherein: said capacitor core fills said cavity, said mold is etched witha combination of hydrogen fluoride vapor and water vapor.
 5. A processin accordance with claim 1 wherein: said capacitor core fills saidcavity, said dopant comprises boron and phosphorus, and said mold isetched with a combination of hydrogen fluoride vapor and water vapor. 6.A process in accordance with claim 1 wherein: said core is a monolithiccore, said monolithic core is planarized by a CMP process which removesa top undoped layer of said mold whereby said monolithic core has a flatupper surface with a rib located at the top of said monolithic core, andetch back said sublayer to separate said monolithic core from adjacentmonolithic cores.
 7. A process of forming an electrode comprising acapacitor core formed on a conductor layer formed on a substrate,forming a mold from a stack of silicon dioxide layers which arealternatingly doped and undoped on said sublayer with said stackcomprising a bottom layer formed on top of said sublayer and eachadditional layer in said stack formed on a previous one of said layersin said stack, patterning said silicon dioxide layers in said mold whichare alternatingly doped and undoped to form an intercore,capacitor-core-shaping cavity in said stack of silicon dioxide layersreaching down through said stack to be bottom of said stack,differentially etching said silicon dioxide layers in said mold formingundercut edges in said doped silicon dioxide layers with said undopedsilicon dioxide layers having cantilevered ribs projecting from saidstacks into said cavity to complete said mold, deposit a thin layer of asecond conductive layer into said cavity forming a thin capacitor corewith counterpart cantilevered ribs with a complementary pattern to saidmold and said capacitor core having a top surface, deposit a layerfilling said inner cavity, polish said capacitor core to remove said topsurface of said core, and remove said photoresist and remove said mold.8. A process in accordance with claim 7 wherein: said mold is etchedwith a combination of hydrogen fluoride vapor and water vapor.
 9. Aprocess in accordance with claim 7 wherein: said dopant comprises boronand phosphorus, and said mold is etched with a combination of hydrogenfluoride vapor and water vapor.
 10. A process in accordance with claim 7wherein: said core is a monolithic core, said monolithic core isplanarized by a CMP process which removes a top undoped layer of saidmold whereby said monolithic core has a flat upper surface with a riblocated on top of said monolithic core, and etch back said sublayer toseparate said monolithic core from adjacent monolithic cores.
 11. Aprocess of forming an electrode comprising a capacitor core formed on asemiconductor device comprising: forming a sublayer of a conductor layerin contact with a plug which contacts a doped region in saidsemiconductor substrate, forming a mold from a stack of silicon dioxidelayers which are alternatingly doped and undoped on said sublayer withsaid stack comprising a bottom layer formed on top of said sublayer andeach additional layer in said stack formed on a previous one of saidlayers in said stack, patterning said silicon dioxide layers in saidmold which are alternatingly doped and undoped to form an intercore,capacitor-core-shaping cavity in said stack of silicon dioxide layersreaching down through said stack to be bottom of said stack,differentially etching said silicon dioxide layers in said mold formingundercut edges in said doped silicon dioxide layers with said undopedsilicon dioxide layers having cantilevered ribs projecting from saidstacks into said cavity to complete said mold, deposit a secondconductive layer into said cavity forming a capacitor core withcounterpart cantilevered ribs with a complementary pattern to said moldand said capacitor core having a top surface, polish said capacitor coreto remove said top surface of said core, and remove said mold.
 12. Aprocess in accordance with claim 11 wherein: said core is a monolithiccore, said monolithic core is planarized by a CMP process which removesa top undoped layer of said mold whereby said monolithic core has a flatupper surface with a rib located on top of said monolithic core, andetch back said sublayer to separate said monolithic core from adjacentmonolithic cores.
 13. A process in accordance with claim 11 wherein:said dopant comprises boron and phosphorus, and etching said mold.
 14. Aprocess in accordance with claim 11 wherein: said capacitor core fillssaid cavity, and etching said mold.
 15. A process in accordance withclaim 11 wherein: said capacitor core fills said cavity, said dopantcomprises boron and phosphorus, and etching said mold with a combinationof hydrogen fluoride vapor and water vapor.
 16. A process in accordancewith claim 11 wherein: etching said mold with a combination of hydrogenfluoride vapor and water vapor.
 17. A process of forming an electrodecomprising a capacitor core formed on a semiconductor device comprising:forming a sublayer of a conductor layer in contact with a plug whichcontacts one of said region in said semiconductor substrate, forming amold from a stack of silicon dioxide layers which are alternatinglydoped and undoped on said sublayer with said stack comprising a bottomlayer formed on top of said sublayer and each additional layer in saidstack formed on a previous one of said layers in said stack, patterningsaid silicon dioxide layers in said mold which are alternatingly dopedand undoped to form an intercore, capacitor-core-shaping cavity in saidstack of silicon dioxide layers reaching down through said stack to bebottom of said stack, differentially etching said silicon dioxide layersin said mold forming undercut edges in said doped silicon dioxide layerswith said undoped silicon dioxide layers having cantilevered ribsprojecting from said stacks into said cavity to complete said mold,deposit a thin layer of a second conductive layer into said cavityforming a thin capacitor core with counterpart cantilevered ribs with acomplementary pattern to said mold and said capacitor core having a topsurface, deposit a layer filling said inner cavity; polish saidcapacitor core to remove said top surface of said core; remove saidphotoresist; and remove said mold.
 18. A process in accordance withclaim 17 wherein: said mold is etched with a combination of hydrogenfluoride vapor and water vapor.
 19. A process in accordance with claim17 wherein: said dopant comprises boron and phosphorus, and said mold isetched with a combination of hydrogen fluoride vapor and water vapor.20. A process in accordance with claim 17 wherein: said core isplanarized by a CMP process which removes a top undoped layer of saidmold whereby said core has a flat upper surface with a rib located ontop of said core, and etch back said sublayer to separate said core fromadjacent cores.
 21. A process in accordance with claim 17 wherein: saidmold is etched with a combination of hydrogen fluoride vapor and watervapor, said second conductive layer is composed of a material selectedfrom the group consisting of aluminum, copper, tungsten, dopedpolysilicon, and titanium nitride, and said second conductive layer hasa thickness from about 500 Å to about 1,000 Å.
 22. A process inaccordance with claim 7 wherein: said dopant comprises boron andphosphorus, and said mold is etched with a combination of hydrogenfluoride vapor and water vapor, said second conductive layer is composedof a material selected from the group consisting of aluminum, copper,tungsten, doped polysilicon, and titanium nitride, and said secondconductive layer has a thickness from about 500 Å to about 1,000 Å. 23.A process in accordance with claim 17 wherein: said second conductivelayer is formed into a monolithic core, said monolithic core isplanarized by a CMP process which removes a top undoped layer of saidmold whereby said monolithic core has a flat upper surface with a riblocated on top of said monolithic core, etch back said sublayer toseparate said monolithic core from adjacent monolithic cores, saidmonolithic core is composed of a material selected from the groupconsisting of aluminum, copper, tungsten, doped polysilicon, andtitanium nitride, and said monolithic core has a thickness from about500 Å to about 1,000 Å.
 24. A monolithic capacitor core formed on asubstrate comprising: a sublayer comprising a first conductive layerformed on said substrate, and a second conductive layer formed into amonolithic monolithic capacitor core having cantilevered ribs projectingfrom exterior sidewalls of said monolithic core.
 25. The monolithiccapacitor core of claim 24 wherein: said second conductive layer isformed into a hollow monolithic capacitor core having cantilevered ribsprojecting from exterior sidewalls of said monolithic core and a basecovering said first conductive layer.
 26. The monolithic capacitor coreof claim 24 wherein: said second conductive layer is formed as a solidmonolithic capacitor core having cantilevered ribs projecting fromexterior sidewalls of said monolithic core and said monolithic corecovering said first conductive layer.
 27. The monolithic capacitor coreof claim 24 wherein: said second conductive layer is composed of amaterial selected from the group consisting of aluminum, copper,tungsten, doped polysilicon, and titanium nitride.
 28. The monolithiccapacitor core of claim 24 wherein: said second conductive layer isformed into a hollow monolithic capacitor core having cantilevered ribsprojecting from exterior sidewalls of said monolithic core and a basecovering said first conductive layer, and said second conductive layeris composed of a material selected from the group consisting ofaluminum, copper, tungsten, doped polysilicon, and titanium nitride. 29.The monolithic capacitor core of claim 24 wherein: said secondconductive layer is formed as a solid monolithic capacitor core havingcantilevered ribs projecting from exterior sidewalls of said monolithiccore, said monolithic core covering said first conductive layer; andsaid second conductive layer is composed of a material selected from thegroup consisting of aluminum, copper, tungsten, doped polysilicon, andtitanium nitride.
 30. The monolithic capacitor core of claim 24 wherein:said second conductive layer is formed into a hollow monolithiccapacitor core having cantilevered ribs projecting from exteriorsidewalls of said monolithic core and a base covering said firstconductive layer, said second conductive layer is composed of a materialselected from the group consisting of aluminum, copper, tungsten, dopedpolysilicon, and titanium nitride, and said second conductive layer hasa thickness from about 500 Å to about 1,000 Å.
 31. A monolithiccapacitor core formed on a semiconductor device comprising: a sublayerfirst conductive layer in contact with a plug which contacts one of saidregion in said semiconductor substrate, a second conductive layer formedinto a monolithic capacitor core having cantilevered ribs projectingfrom exterior sidewalls of said monolithic core, said monolithiccapacitor core having a cantilevered top surface projecting from saidexterior sidewall of said monolithic core.
 32. The monolithic capacitorcore of claim 31 wherein: said second conductive layer is formed into ahollow monolithic capacitor core having cantilevered ribs projectingfrom exterior sidewalls of said monolithic core and a base covering saidfirst conductive layer.
 33. The monolithic capacitor core of claim 31wherein: said second conductive layer is formed as a solid monolithiccapacitor core with cantilevered ribs projecting from exterior sidewallsof said monolithic core and said monolithic core covering said firstconductive layer.
 34. The monolithic capacitor core of claim 31 wherein:said second conductive layer is composed of a material selected from thegroup consisting of aluminum, copper, tungsten, doped polysilicon, andtitanium nitride.
 35. The monolithic capacitor core of claim 31 wherein:said second conductive layer is formed into a hollow monolithiccapacitor core having cantilevered ribs projecting from exteriorsidewalls of said monolithic core and a base covering said firstconductive layer, and said second conductive layer is composed of amaterial selected from the group consisting of aluminum, copper,tungsten, doped polysilicon, and titanium nitride.
 36. The monolithiccapacitor core of claim 31 wherein: said second conductive layer isformed as a solid monolithic capacitor core having cantilevered ribsprojecting from exterior sidewalls of said monolithic core and saidmonolithic core covering said first conductive layer, and said secondconductive layer is composed of a material selected from the groupconsisting of aluminum, copper, tungsten, doped polysilicon, andtitanium nitride.
 37. The monolithic capacitor core of claim 31 wherein:said second conductive layer is formed into a hollow monolithiccapacitor core having cantilevered ribs projecting from exteriorsidewalls of said monolithic core and a base covering said firstconductive layer, said second conductive layer is composed of a materialselected from the group consisting of aluminum, copper, tungsten, dopedpolysilicon, and titanium nitride, and said second conductive layer hasa thickness from about 500 Å to about 1,000 Å.
 38. The monolithiccapacitor core of claim 31 wherein: said second conductive layer isformed as a plurality of solid monolithic capacitor cores having saidcantilevered ribs projecting from exterior sidewalls of said monolithiccore and said monolithic core covering said first conductive layer, saidsecond conductive layer is composed of a material selected from thegroup consisting of aluminum, copper, tungsten, doped polysilicon, andtitanium nitride, and said sublayer having been formed into separatedportions isolating said monolithic cores from adjacent ones of saidmonolithic cores.
 39. The monolithic capacitor core of claim 31 wherein:said second conductive layer is formed as a plurality of hollowmonolithic capacitor cores having said cantilevered ribs projecting fromexterior sidewalls of said monolithic core and said monolithic corecovering said first conductive layer, said second conductive layer iscomposed of a material selected from the group consisting of aluminum,copper, tungsten, doped polysilicon, and titanium nitride, and saidsublayer having been formed into separated portions isolating saidmonolithic cores from adjacent ones of said monolithic cores.